1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a control circuit for a clock signal.
2. Description of Related Art
A synchronous delay circuit capable of removing a clock skew in a synchronizing time of a short time length, is used in a high speed synchronous circuit, from the viewpoint of a simple circuit construction and a small current consumption. As regards the prior art of the synchronous delay circuit, the following documents can be referred to:
(1) Japanese Patent Application Pre-examination Publication No. JP-A-08-237091 (corresponding to European Patent Application Pre-examination Publication No. EP-0 720 291-A2) PA0 (2) Toshio Yamada et al, "Capacitance coupled Bus with Negative Delay Circuit for High Speed and Low Power (10 GB/s&lt;500 mW) Synchronous DRAMs", 1996 Symp. on VLSI Circ. pp.112-113 PA0 (3) Jim-Man Han et al, "Skew Minimization Technique for 256M-bit Synchronous DRAM and beyond", 1996 Symp. on VLSI Circ. pp.192-193 PA0 (4) Richard B. Watson et al, "Clock Buffer Chip with Absolute Delay Regulation Over Process and Environment Variations", Proc. of IEEE 1992 CICC (Custom Integrated Circuits Conference) 25.2 PA0 (5) Yoshinori OKAJIMA et al, "Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface", IEICE TRANS. ELECTRON., VOL.E79-C, NO.6, June 1996 pp.798-807.
The content of the above documents are incorporated by reference in its entirety into this application.
A basic construction of the prior art synchronous delay circuit is shown in FIG. 9. Referring to FIG. 9, the prior art synchronous delay circuit includes two delay circuit arrays composed of a delay circuit array 901 used for measuring a predetermined time difference and a delay circuit array 902 for reproducing the measured delay time, and also includes a dummy delay circuit 905 having a delay time td1+td2 corresponding to the sum of respective delay times td1 and td2 of an input buffer 903 and a clock driver 904. In many cases, as shown in FIG. 9, the dummy delay circuit 905 includes an input buffer dummy 905A which is completely the same as that input buffer, and a clock driver dummy 905B, in order to equalize the delay time equal to the delay times td1 and td2 of the input buffer 903 and the clock driver 904.
Now, classification of the prior art synchronous delay circuit will be described. The delay circuit array 901 and the delay circuit array 902 are formed of delay circuit arrays having the same delay time. The purpose of the delay circuit array 901 and the delay circuit array 902 is to measure a predetermined period of time by means of the delay circuit array 901 and to reproduce the predetermined of time by means of the delay circuit array 902. Namely, during a period of time to be measured, a signal is progressed in the delay circuit array 901, and a period of time equal to the measuring period is reproduced by causing a signal to pass through delay elements of the same number as that of the delay elements through which the first named signal has progressed.
A system in which a signal is caused to pass in the delay circuit array 902 the delay elements of the same number as that of the delay elements through which a signal has progressed in the delay circuit array 901, can be classified to two, on the basis of the signal progressing directions of the delay circuit array 901 and the delay circuit array 902. In addition, this system can also divided into two, on the basis of which of an end of the path and the whole of the path is selected for determining the length of the delay circuit array 902. Therefore, it can be classified into four types.
Namely, if the system is classified on the basis of the signal progressing directions of the delay circuit array 901 and the delay circuit array 902, it is classified into one in which as shown in FIG. 12 and FIG. 13, the respective signal progressing directions of the delay circuit array 901 and the delay circuit array 902 are the same, and the number of delay elements in the delay circuit arrays 902 is determined by an output terminal side of the delay circuit array 902, and another in which as shown in FIG. 10 and FIG. 11, the respective signal progressing directions of the delay circuit array 901 and the delay circuit array 902 are opposite to each other, and the number of delay elements in the delay circuit arrays 902 is determined by an input terminal side of the delay circuit array 902,
As regard which of an end of the path and the whole of the path is selected for determining the length of the delay circuit array 902, it is classified into a system for selecting the end of the path as shown in FIGS. 10 and 11, and another system for selecting the whole of the path shown in FIGS. 12 and 13.
FIG. 10 corresponds to the system shown in JP-A-08-237091 (EP-0 720 291-A2), and FIG. 11 corresponds to the system shown in the above referred document (5) IEICE TRANS. ELECTRON., VOL.E79-C, NO.6, June 1996 pp.798-807. FIG. 12 corresponds to the above referred document (3) 1996 Symp. on VLSI Circ. pp.192-193, and FIG. 13 corresponds to the above referred document (2) 1996 Symp. on VLSI Circ. pp.112-113 and the above referred document (4) Proc. of IEEE 1992 CICC (Custom Integrated Circuits Conference) 25.2.
Now, an operation of the prior art synchronous delay circuit will be described.
An operation for removing a clock skew will be described with reference to FIGS. 14A and 14B and FIGS. 15A and 15B.
(1) Clock delay in the case of using a synchronous delay circuit
In the circuit shown in FIG. 14A using no synchronous delay circuit, an external clock 906 passes through an input buffer 903 and a clock driver 904, and is outputted as an internal clock 907. In this process, a time difference between the external clock and the internal clock is a sum of a delay time td1 of the input buffer 903 and a delay time td2 of the clock driver 904. Namely, td1+td2 becomes the clock skew.
(2) Principle for removing the clock delay in the case of using a synchronous delay circuit
In order to effectively remove this clock skew, the synchronous delay circuit utilizes the feature that the clock pulse is inputted at every clock period tcK. Namely, a delay circuit having a delay time of tcK-(td1+td2) is prepared, and the delay circuit is located between the input buffer (having the delay time td1) and the clock driver (having the delay time td2), so that a total delay time becomes the clock period tcK (=td1+tcK-(td1+td2)+td2). As a result, the timing of the internal clock outputted from the clock driver becomes equal to the timing of the external clock.
(3) Method for removing the clock delay in the case of using a synchronous delay circuit
The synchronous delay circuit shown in FIG. 15A is the same circuit construction as that shown in FIG. 9, and FIG. 15B shows a timing chart for illustrating an operation of the synchronous delay circuit. In FIG. 15B, "A", "B" and "C" show signal waveforms on an output of the input buffer 903, an output of the dummy delay circuit 905 and an output node of the second delay circuit 902, respectively.
The operation of the synchronous delay circuit requires two periods. A first period is used to measure the delay time tcK-(td1+td2) depending upon the clock period, and to determine the delay length of the delay circuit for reproducing the delay amount of tcK-(td1+td2). A second period is used for use the obtained delay amount of tcK-(td1+td2).
First, in the first delay time, in order to measure the delay time tcK-(td1+td2) depending upon the clock period, the dummy delay circuit 905 of the clock driver 904 and the delay circuit array 901 are used. During one clock period tcK from the moment a first pulse of two continuous pulses of the external pulse 906 is outputted from the input buffer 903 to the moment a second pulse of the two continuous pulses synchronous delay circuit is outputted from the input buffer 903, a clock is caused to progress in the dummy delay circuit 905 and the delay circuit array 901.
Since the delay time of the dummy delay circuit 905 is td1-td2, the time by which the pulse progresses in the delay circuit array 901 becomes tcK-(td1+td2).
Therefore, the delay time of the delay circuit array 902 is set to become equal to tcK-(td1+td2) by the pulse progresses in the delay circuit array 901.
The method for setting this delay time of the delay circuit array 902 is generally divided into four as mentioned above, but a desired object can be achieved by each of the four method.
In the next period, the clock outputted from the input buffer 903 passes through the delay circuit 903 having the delay time of tcK-(td1+td2), and outputted from the clock driver 903 so that an internal clock having the delay time tcK is generated.
In the above mentioned process, the internal clock 907 having no clock skew is generated with two clock periods.
In the above mentioned prior art synchronous delay circuits, since the dummy delay amount of the clock is fixed, it is necessary to estimate the fixed delay amount. Therefore, in a device such as a microprocessor and a memory device capable of previously estimating the clock delay amount, since the design of transistors to interconnections is carried out in bundle, it is relatively easy to design the clock driver dummy.
However, in the case of using the synchronous delay circuit as a macro in ASIC (application specific integrated circuit), a transistor gate process for designing the dummy delay circuit and an interconnection process dominating an actual clock delay are separate in design, so that the clock delay amount is different from one interconnection design used in the chip to another. In this device, it is difficult to design the clock dummy delay circuit, and therefore, it becomes necessary to design the dummy delay circuit after the interconnection are located. As a result, the efficiency is very bad.
Accordingly, the pattern previously designed as the macro becomes only the delay circuit array 901 and the delay circuit array 902, and therefore, it is necessary to ensure a region for the dummy clock driver 905B in a layout. This is very uneconomical.
In addition, even in the device such as the microprocessor and the memory device capable of previously estimating the clock delay amount, the delay amount of the clock driver dummy and the delay amount of the clock driver have a difference in a temperature dependency of the delay time and in a temperature dependency of a power supply voltage, as shown in FIGS. 16A and 16B, and it is very difficult to make these characteristics completely coincident with each other. Accordingly, the difference between the delay amount of the clock driver dummy and the delay amount of the original clock driver becomes an error in the skew removal.